a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
This repository belongs to UltraMIPS_NSCSCC, and consists of the development of pipeline Cache(ICache/DCache) and associated components for dual-issue cpu.
Asymmetric dual issue in-order microprocessor.
MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
Naïve MIPS32 SoC implementation