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数字电路实验的Vivado项目。

2021秋数电实验。

a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog

This repository belongs to UltraMIPS_NSCSCC, and consists of the development of pipeline Cache(ICache/DCache) and associated components for dual-issue cpu.

Asymmetric dual issue in-order microprocessor.

MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support

NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

MIPS CPU

USTC NSCSCC-2020-1

Naïve MIPS32 SoC implementation

2021秋季学期体系结构实验

2021秋季学期体系结构实验

2021秋季学期体系结构实验

2021秋季学期体系结构实验