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Commit d3016199 authored by jinbao chen's avatar jinbao chen
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finish fifo

parent 2387eb71
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lab2/SourceCode/Cache/InstCacheQS.v 0 → 100644
View file @ d3016199
// asm file name: .\QuickSort.S
module InstructionCache(
input wire clk,
input wire write_en,
input wire [31:2] addr, debug_addr,
input wire [31:0] debug_input,
output reg [31:0] data, debug_data
);
// local variable
wire addr_valid = (addr[31:14] == 18'h0);
wire debug_addr_valid = (debug_addr[31:14] == 18'h0);
wire [11:0] dealt_addr = addr[13:2];
wire [11:0] dealt_debug_addr = debug_addr[13:2];
// cache content
reg [31:0] inst_cache[0:4095];
initial begin
data = 32'h0;
debug_data = 32'h0;
inst_cache[ 0] = 32'h10004693;
inst_cache[ 1] = 32'h00001137;
inst_cache[ 2] = 32'h00004533;
inst_cache[ 3] = 32'h000045b3;
inst_cache[ 4] = 32'hfff68613;
inst_cache[ 5] = 32'h00261613;
inst_cache[ 6] = 32'h024000ef;
inst_cache[ 7] = 32'h00068293;
inst_cache[ 8] = 32'h00050313;
inst_cache[ 9] = 32'h00229293;
inst_cache[ 10] = 32'h00231313;
inst_cache[ 11] = 32'h00032383;
inst_cache[ 12] = 32'h00430313;
inst_cache[ 13] = 32'hfe534ce3;
inst_cache[ 14] = 32'h0000006f;
inst_cache[ 15] = 32'h0cc5da63;
inst_cache[ 16] = 32'h0005e333;
inst_cache[ 17] = 32'h000663b3;
inst_cache[ 18] = 32'h006502b3;
inst_cache[ 19] = 32'h0002a283;
inst_cache[ 20] = 32'h04735263;
inst_cache[ 21] = 32'h00750e33;
inst_cache[ 22] = 32'h000e2e03;
inst_cache[ 23] = 32'h005e4663;
inst_cache[ 24] = 32'hffc38393;
inst_cache[ 25] = 32'hfedff06f;
inst_cache[ 26] = 32'h00650eb3;
inst_cache[ 27] = 32'h01cea023;
inst_cache[ 28] = 32'h02735263;
inst_cache[ 29] = 32'h00650e33;
inst_cache[ 30] = 32'h000e2e03;
inst_cache[ 31] = 32'h01c2c663;
inst_cache[ 32] = 32'h00430313;
inst_cache[ 33] = 32'hfedff06f;
inst_cache[ 34] = 32'h00750eb3;
inst_cache[ 35] = 32'h01cea023;
inst_cache[ 36] = 32'hfc7340e3;
inst_cache[ 37] = 32'h00650eb3;
inst_cache[ 38] = 32'h005ea023;
inst_cache[ 39] = 32'hffc10113;
inst_cache[ 40] = 32'h00112023;
inst_cache[ 41] = 32'hffc10113;
inst_cache[ 42] = 32'h00b12023;
inst_cache[ 43] = 32'hffc10113;
inst_cache[ 44] = 32'h00c12023;
inst_cache[ 45] = 32'hffc10113;
inst_cache[ 46] = 32'h00612023;
inst_cache[ 47] = 32'hffc30613;
inst_cache[ 48] = 32'hf7dff0ef;
inst_cache[ 49] = 32'h00012303;
inst_cache[ 50] = 32'h00410113;
inst_cache[ 51] = 32'h00012603;
inst_cache[ 52] = 32'h00410113;
inst_cache[ 53] = 32'h00012583;
inst_cache[ 54] = 32'hffc10113;
inst_cache[ 55] = 32'h00c12023;
inst_cache[ 56] = 32'hffc10113;
inst_cache[ 57] = 32'h00612023;
inst_cache[ 58] = 32'h00430593;
inst_cache[ 59] = 32'hf51ff0ef;
inst_cache[ 60] = 32'h00012303;
inst_cache[ 61] = 32'h00410113;
inst_cache[ 62] = 32'h00012603;
inst_cache[ 63] = 32'h00410113;
inst_cache[ 64] = 32'h00012583;
inst_cache[ 65] = 32'h00410113;
inst_cache[ 66] = 32'h00012083;
inst_cache[ 67] = 32'h00410113;
inst_cache[ 68] = 32'h00008067;
end
always@(posedge clk)
begin
data <= addr_valid ? inst_cache[dealt_addr] : 32'h0;
debug_data <= debug_addr_valid ? inst_cache[dealt_debug_addr] : 32'h0;
if(write_en & debug_addr_valid)
inst_cache[dealt_debug_addr] <= debug_input;
end
endmodule
lab2/SourceCode/Cache/memQS.sv 0 → 100644
View file @ d3016199
module mem #( //
parameter ADDR_LEN = 11 //
) (
input clk, rst,
input [ADDR_LEN-1:0] addr, // memory address
output reg [31:0] rd_data, // data read out
input wr_req,
input [31:0] wr_data // data write in
);
localparam MEM_SIZE = 1<<ADDR_LEN;
reg [31:0] ram_cell [MEM_SIZE];
always @ (posedge clk or posedge rst)
if(rst)
rd_data <= 0;
else
rd_data <= ram_cell[addr];
always @ (posedge clk)
if(wr_req)
ram_cell[addr] <= wr_data;
initial begin
ram_cell[ 0] = 32'h0000001c;
ram_cell[ 1] = 32'h00000007;
ram_cell[ 2] = 32'h00000053;
ram_cell[ 3] = 32'h00000029;
ram_cell[ 4] = 32'h00000000;
ram_cell[ 5] = 32'h00000050;
ram_cell[ 6] = 32'h00000079;
ram_cell[ 7] = 32'h00000087;
ram_cell[ 8] = 32'h000000cd;
ram_cell[ 9] = 32'h00000058;
ram_cell[ 10] = 32'h000000c5;
ram_cell[ 11] = 32'h0000008b;
ram_cell[ 12] = 32'h0000009f;
ram_cell[ 13] = 32'h0000003a;
ram_cell[ 14] = 32'h0000003b;
ram_cell[ 15] = 32'h00000035;
ram_cell[ 16] = 32'h00000041;
ram_cell[ 17] = 32'h0000009a;
ram_cell[ 18] = 32'h0000009d;
ram_cell[ 19] = 32'h00000001;
ram_cell[ 20] = 32'h0000001a;
ram_cell[ 21] = 32'h0000006f;
ram_cell[ 22] = 32'h000000d2;
ram_cell[ 23] = 32'h0000008f;
ram_cell[ 24] = 32'h00000099;
ram_cell[ 25] = 32'h000000dc;
ram_cell[ 26] = 32'h0000007f;
ram_cell[ 27] = 32'h0000006b;
ram_cell[ 28] = 32'h000000ce;
ram_cell[ 29] = 32'h0000005e;
ram_cell[ 30] = 32'h0000004d;
ram_cell[ 31] = 32'h00000032;
ram_cell[ 32] = 32'h0000002e;
ram_cell[ 33] = 32'h00000013;
ram_cell[ 34] = 32'h0000004f;
ram_cell[ 35] = 32'h000000c6;
ram_cell[ 36] = 32'h00000019;
ram_cell[ 37] = 32'h000000ed;
ram_cell[ 38] = 32'h00000089;
ram_cell[ 39] = 32'h000000f8;
ram_cell[ 40] = 32'h000000be;
ram_cell[ 41] = 32'h000000da;
ram_cell[ 42] = 32'h00000080;
ram_cell[ 43] = 32'h0000002f;
ram_cell[ 44] = 32'h00000097;
ram_cell[ 45] = 32'h00000061;
ram_cell[ 46] = 32'h00000026;
ram_cell[ 47] = 32'h00000017;
ram_cell[ 48] = 32'h00000055;
ram_cell[ 49] = 32'h000000c4;
ram_cell[ 50] = 32'h000000aa;
ram_cell[ 51] = 32'h00000008;
ram_cell[ 52] = 32'h000000d9;
ram_cell[ 53] = 32'h00000018;
ram_cell[ 54] = 32'h00000095;
ram_cell[ 55] = 32'h00000085;
ram_cell[ 56] = 32'h000000a0;
ram_cell[ 57] = 32'h0000004c;
ram_cell[ 58] = 32'h00000076;
ram_cell[ 59] = 32'h0000004e;
ram_cell[ 60] = 32'h000000fd;
ram_cell[ 61] = 32'h00000083;
ram_cell[ 62] = 32'h0000008a;
ram_cell[ 63] = 32'h000000a2;
ram_cell[ 64] = 32'h0000005d;
ram_cell[ 65] = 32'h00000009;
ram_cell[ 66] = 32'h00000062;
ram_cell[ 67] = 32'h00000006;
ram_cell[ 68] = 32'h000000af;
ram_cell[ 69] = 32'h000000a6;
ram_cell[ 70] = 32'h000000f1;
ram_cell[ 71] = 32'h000000d7;
ram_cell[ 72] = 32'h00000072;
ram_cell[ 73] = 32'h000000c1;
ram_cell[ 74] = 32'h000000e1;
ram_cell[ 75] = 32'h000000cc;
ram_cell[ 76] = 32'h0000007e;
ram_cell[ 77] = 32'h00000039;
ram_cell[ 78] = 32'h00000048;
ram_cell[ 79] = 32'h0000002d;
ram_cell[ 80] = 32'h000000bb;
ram_cell[ 81] = 32'h0000007c;
ram_cell[ 82] = 32'h00000004;
ram_cell[ 83] = 32'h000000bf;
ram_cell[ 84] = 32'h00000059;
ram_cell[ 85] = 32'h000000bd;
ram_cell[ 86] = 32'h000000df;
ram_cell[ 87] = 32'h0000007b;
ram_cell[ 88] = 32'h00000049;
ram_cell[ 89] = 32'h0000000c;
ram_cell[ 90] = 32'h0000008c;
ram_cell[ 91] = 32'h000000f3;
ram_cell[ 92] = 32'h000000e7;
ram_cell[ 93] = 32'h00000073;
ram_cell[ 94] = 32'h00000057;
ram_cell[ 95] = 32'h0000001b;
ram_cell[ 96] = 32'h00000052;
ram_cell[ 97] = 32'h00000086;
ram_cell[ 98] = 32'h00000077;
ram_cell[ 99] = 32'h000000e4;
ram_cell[ 100] = 32'h000000a7;
ram_cell[ 101] = 32'h0000005f;
ram_cell[ 102] = 32'h000000f4;
ram_cell[ 103] = 32'h00000024;
ram_cell[ 104] = 32'h00000042;
ram_cell[ 105] = 32'h00000071;
ram_cell[ 106] = 32'h000000eb;
ram_cell[ 107] = 32'h000000f9;
ram_cell[ 108] = 32'h000000b5;
ram_cell[ 109] = 32'h000000c7;
ram_cell[ 110] = 32'h00000065;
ram_cell[ 111] = 32'h00000005;
ram_cell[ 112] = 32'h00000067;
ram_cell[ 113] = 32'h00000063;
ram_cell[ 114] = 32'h00000069;
ram_cell[ 115] = 32'h00000075;
ram_cell[ 116] = 32'h00000064;
ram_cell[ 117] = 32'h000000ab;
ram_cell[ 118] = 32'h000000f2;
ram_cell[ 119] = 32'h000000ef;
ram_cell[ 120] = 32'h00000011;
ram_cell[ 121] = 32'h00000010;
ram_cell[ 122] = 32'h00000098;
ram_cell[ 123] = 32'h00000020;
ram_cell[ 124] = 32'h00000088;
ram_cell[ 125] = 32'h00000033;
ram_cell[ 126] = 32'h0000002c;
ram_cell[ 127] = 32'h000000d6;
ram_cell[ 128] = 32'h000000d5;
ram_cell[ 129] = 32'h0000002b;
ram_cell[ 130] = 32'h000000fe;
ram_cell[ 131] = 32'h000000cb;
ram_cell[ 132] = 32'h0000001e;
ram_cell[ 133] = 32'h00000066;
ram_cell[ 134] = 32'h00000021;
ram_cell[ 135] = 32'h00000027;
ram_cell[ 136] = 32'h00000025;
ram_cell[ 137] = 32'h0000001f;
ram_cell[ 138] = 32'h000000ad;
ram_cell[ 139] = 32'h00000093;
ram_cell[ 140] = 32'h000000fa;
ram_cell[ 141] = 32'h0000004b;
ram_cell[ 142] = 32'h00000046;
ram_cell[ 143] = 32'h00000028;
ram_cell[ 144] = 32'h000000a3;
ram_cell[ 145] = 32'h00000002;
ram_cell[ 146] = 32'h00000051;
ram_cell[ 147] = 32'h00000078;
ram_cell[ 148] = 32'h0000007d;
ram_cell[ 149] = 32'h00000082;
ram_cell[ 150] = 32'h000000ea;
ram_cell[ 151] = 32'h000000e8;
ram_cell[ 152] = 32'h0000003c;
ram_cell[ 153] = 32'h000000e0;
ram_cell[ 154] = 32'h0000006e;
ram_cell[ 155] = 32'h00000030;
ram_cell[ 156] = 32'h0000006d;
ram_cell[ 157] = 32'h000000fb;
ram_cell[ 158] = 32'h000000ec;
ram_cell[ 159] = 32'h000000bc;
ram_cell[ 160] = 32'h00000014;
ram_cell[ 161] = 32'h0000003d;
ram_cell[ 162] = 32'h0000000f;
ram_cell[ 163] = 32'h0000009e;
ram_cell[ 164] = 32'h000000d4;
ram_cell[ 165] = 32'h00000091;
ram_cell[ 166] = 32'h000000b7;
ram_cell[ 167] = 32'h000000c3;
ram_cell[ 168] = 32'h00000043;
ram_cell[ 169] = 32'h0000002a;
ram_cell[ 170] = 32'h0000005b;
ram_cell[ 171] = 32'h000000e9;
ram_cell[ 172] = 32'h00000074;
ram_cell[ 173] = 32'h0000007a;
ram_cell[ 174] = 32'h00000036;
ram_cell[ 175] = 32'h000000f0;
ram_cell[ 176] = 32'h000000b0;
ram_cell[ 177] = 32'h000000ff;
ram_cell[ 178] = 32'h000000b6;
ram_cell[ 179] = 32'h00000015;
ram_cell[ 180] = 32'h00000038;
ram_cell[ 181] = 32'h0000008e;
ram_cell[ 182] = 32'h000000c9;
ram_cell[ 183] = 32'h000000f7;
ram_cell[ 184] = 32'h000000d0;
ram_cell[ 185] = 32'h0000009c;
ram_cell[ 186] = 32'h000000b8;
ram_cell[ 187] = 32'h00000034;
ram_cell[ 188] = 32'h0000006c;
ram_cell[ 189] = 32'h000000d3;
ram_cell[ 190] = 32'h00000045;
ram_cell[ 191] = 32'h00000047;
ram_cell[ 192] = 32'h000000b3;
ram_cell[ 193] = 32'h000000d1;
ram_cell[ 194] = 32'h000000b4;
ram_cell[ 195] = 32'h00000040;
ram_cell[ 196] = 32'h000000dd;
ram_cell[ 197] = 32'h0000005a;
ram_cell[ 198] = 32'h000000a8;
ram_cell[ 199] = 32'h000000e6;
ram_cell[ 200] = 32'h0000005c;
ram_cell[ 201] = 32'h00000068;
ram_cell[ 202] = 32'h00000054;
ram_cell[ 203] = 32'h0000004a;
ram_cell[ 204] = 32'h0000009b;
ram_cell[ 205] = 32'h00000003;
ram_cell[ 206] = 32'h000000d8;
ram_cell[ 207] = 32'h000000a9;
ram_cell[ 208] = 32'h0000003f;
ram_cell[ 209] = 32'h00000056;
ram_cell[ 210] = 32'h0000001d;
ram_cell[ 211] = 32'h00000022;
ram_cell[ 212] = 32'h000000cf;
ram_cell[ 213] = 32'h00000031;
ram_cell[ 214] = 32'h0000000b;
ram_cell[ 215] = 32'h000000db;
ram_cell[ 216] = 32'h000000a5;
ram_cell[ 217] = 32'h00000094;
ram_cell[ 218] = 32'h000000f6;
ram_cell[ 219] = 32'h000000c0;
ram_cell[ 220] = 32'h00000084;
ram_cell[ 221] = 32'h00000012;
ram_cell[ 222] = 32'h000000e2;
ram_cell[ 223] = 32'h0000006a;
ram_cell[ 224] = 32'h000000ac;
ram_cell[ 225] = 32'h0000000e;
ram_cell[ 226] = 32'h000000f5;
ram_cell[ 227] = 32'h0000000a;
ram_cell[ 228] = 32'h000000a1;
ram_cell[ 229] = 32'h00000081;
ram_cell[ 230] = 32'h000000a4;
ram_cell[ 231] = 32'h000000c8;
ram_cell[ 232] = 32'h000000de;
ram_cell[ 233] = 32'h0000000d;
ram_cell[ 234] = 32'h000000ca;
ram_cell[ 235] = 32'h00000096;
ram_cell[ 236] = 32'h000000b2;
ram_cell[ 237] = 32'h00000044;
ram_cell[ 238] = 32'h000000e5;
ram_cell[ 239] = 32'h00000092;
ram_cell[ 240] = 32'h000000ee;
ram_cell[ 241] = 32'h000000ba;
ram_cell[ 242] = 32'h00000023;
ram_cell[ 243] = 32'h00000037;
ram_cell[ 244] = 32'h00000090;
ram_cell[ 245] = 32'h000000b9;
ram_cell[ 246] = 32'h0000008d;
ram_cell[ 247] = 32'h000000c2;
ram_cell[ 248] = 32'h00000016;
ram_cell[ 249] = 32'h000000ae;
ram_cell[ 250] = 32'h000000b1;
ram_cell[ 251] = 32'h000000e3;
ram_cell[ 252] = 32'h000000fc;
ram_cell[ 253] = 32'h00000070;
ram_cell[ 254] = 32'h0000003e;
ram_cell[ 255] = 32'h00000060;
end
endmodule
lab2/SourceCode/ControlUnit.v
View file @ d3016199
......@@ -54,7 +54,8 @@ module ControlUnit(
output reg AluOutSrc,
output reg CSRWriteD,
output reg [1:0] CSRAluCtlD,
output reg CSRRead
output reg CSRRead,
output reg MemReadD
);
reg RJalD,RJalrD,RMemToRegD,RLoadNpcD,RAluSrc1D;
reg [1:0] RAluSrc2D;
......@@ -69,6 +70,7 @@ if(Op==7'b1110011)begin//csr
ImmType <= `ZTYPE;
AluContrlD <= 4'd11;
AluOutSrc <= 1'b1;
MemReadD <= 1'b0;
case(Fn3)
3'b001:begin//csrrw
RegReadD <= 2'b10;
......@@ -142,6 +144,7 @@ begin
BranchTypeD <= `NOBRANCH;
MemWriteD <= 4'b0000;//32bit
ImmType <= `RTYPE;
MemReadD <= 1'b0;
case(Fn3)
3'b000:begin
case(Fn7)
......@@ -273,6 +276,7 @@ begin
endcase
end
7'b0010011:begin//Itype
MemReadD <= 1'b0;
if(Fn3==3'b001)
begin
{RJalD,RJalrD,RMemToRegD,RLoadNpcD,RAluSrc1D} <= 5'b00000;
......@@ -375,6 +379,7 @@ begin
RegReadD <= 2'b11;//rs1 rs2
ImmType <= `STYPE;
AluContrlD <= `ADD;
MemReadD <= 1'b0;
case(Fn3)
3'b000:begin//store byte
MemWriteD <= 4'b0001;
......@@ -399,6 +404,7 @@ begin
RegReadD <= 2'b10;//rs1
ImmType <= `ITYPE;
AluContrlD <= `ADD;
MemReadD <= 1'b1;
case(Fn3)
3'b000:begin//load byte
RegWriteD <= `LB;
......@@ -427,6 +433,7 @@ begin
RegReadD <= 2'b11;//rs1 rs2
ImmType <= `BTYPE;
AluContrlD <= 4'd11;
MemReadD <= 1'b0;
case(Fn3)
3'b000:begin
BranchTypeD <= `BEQ;
......@@ -460,6 +467,7 @@ begin
RegReadD <= 2'b10;//rs1
ImmType <= `ITYPE;
AluContrlD <= `ADD;
MemReadD <= 1'b0;
end
7'b1101111:begin//jal
{RJalD,RJalrD,RMemToRegD,RLoadNpcD,RAluSrc1D} <= 5'b10010;
......@@ -470,6 +478,7 @@ begin
RegReadD <= 2'b00;//
ImmType <= `JTYPE;
AluContrlD <= 4'd11;
MemReadD <= 1'b0;
end
7'b0010111:begin//AUIPC
{RJalD,RJalrD,RMemToRegD,RLoadNpcD,RAluSrc1D} <= 5'b00001;
......@@ -480,6 +489,7 @@ begin
RegReadD <= 2'b00;//
ImmType <= `UTYPE;
AluContrlD <= `ADD;
MemReadD <= 1'b0;
end
7'b0110111:begin
{RJalD,RJalrD,RMemToRegD,RLoadNpcD,RAluSrc1D} <= 5'b00000;
......@@ -490,6 +500,7 @@ begin
RegReadD <= 2'b00;//
ImmType <= `UTYPE;
AluContrlD <= `LUI;
MemReadD <= 1'b0;
end
default:begin
{RJalD,RJalrD,RMemToRegD,RLoadNpcD,RAluSrc1D} <= 5'b00000;
......@@ -500,6 +511,7 @@ begin
RegReadD <= 2'b00;//
ImmType <= `RTYPE;
AluContrlD <= 4'd11;
MemReadD <= 1'b0;
end
endcase
end
......
lab2/SourceCode/EXSegReg.v
View file @ d3016199
......@@ -69,7 +69,9 @@ module EXSegReg(
input wire [31:0] CSROutD,
output reg [31:0] CSROutE,
input wire CSRRead,
output reg CSRReadE
output reg CSRReadE,
input wire MemReadD,
output reg MemReadE
);
initial begin
PCE = 32'b0;
......@@ -97,6 +99,7 @@ module EXSegReg(
CSRRdE = 12'b0;
CSROutE = 32'b0;
CSRReadE = 1'b0;
MemReadE = 1'b0;
end
//
always@(posedge clk) begin
......@@ -110,6 +113,7 @@ module EXSegReg(
CSRRdE <= 12'b0;
CSROutE <= 32'b0;
CSRReadE <= 1'b0;
MemReadE <= 1'b0;
PCE<=32'b0;
BrNPC<=32'b0;
ImmE<=32'b0;
......@@ -136,6 +140,7 @@ module EXSegReg(
CSRRdE <= CSRRdD;
CSROutE <= CSROutD;
CSRReadE <= CSRRead;
MemReadE <= MemReadD;
PCE<=PCD;
BrNPC<=JalNPC;
ImmE<=ImmD;
......
lab2/SourceCode/HarzardUnit.v
View file @ d3016199
......@@ -59,6 +59,11 @@ always@(*) begin //checking jump and hazard
{FlushF, FlushD, FlushE, FlushM, FlushW} <= 5'b11111;
{StallF, StallD, StallE, StallM, StallW} <= 5'b00000;
end
else begin
if(DCacheMiss)begin
{FlushF, FlushD, FlushE, FlushM, FlushW} <= 5'b00000;
{StallF, StallD, StallE, StallM, StallW} <= 5'b11111;
end
else begin
if(BranchE)begin
{FlushF, FlushD, FlushE, FlushM, FlushW} <= 5'b01100;
......@@ -74,7 +79,7 @@ always@(*) begin //checking jump and hazard
end
else begin
if(MemToRegE)begin
if(Rs1D==RdE||Rs2D==RdE&&RdE!=5'b00000) begin//hazard detected
if((Rs1D==RdE||Rs2D==RdE)&&RdE!=5'b00000) begin//hazard detected
{FlushF, FlushD, FlushE, FlushM, FlushW} <= 5'b00100;
{StallF, StallD, StallE, StallM, StallW} <= 5'b11000;
end
......@@ -87,7 +92,8 @@ always@(*) begin //checking jump and hazard
{FlushF, FlushD, FlushE, FlushM, FlushW} <= 5'b00000;
{StallF, StallD, StallE, StallM, StallW} <= 5'b00000;
end
end
end
end
end
end
......
lab2/SourceCode/IDSegReg.v
View file @ d3016199
......@@ -54,7 +54,7 @@ module IDSegReg(
PCD <= clear ? 0: PCF;
wire [31:0] RD_raw;
InstructionRam InstructionRamInst (
/* InstructionRam InstructionRamInst (
.clk (clk), //请完善代码
.addra (A[31:2]), //请完善代码
.douta ( RD_raw ),
......@@ -62,7 +62,17 @@ module IDSegReg(
.addrb ( A2[31:2] ),
.dinb ( WD2 ),
.doutb ( RD2 )
);
); */
InstructionCache InstCacheInst (
.clk(clk),
.write_en(|WE2),
.addr(A[31:2]),
.debug_addr(A2[31:2]),
.debug_input(WD2),
.data(RD_raw),
.debug_data(RD2)
);
// Add clear and stall support
// if chip not enabled, output output last read result
// else if chip clear, output 0
......@@ -75,7 +85,7 @@ module IDSegReg(
begin
stall_ff<=~en;
clear_ff<=clear;
RD_old<=RD_raw;
RD_old<=RD;
end
assign RD = stall_ff ? RD_old : (clear_ff ? 32'b0 : RD_raw );
......
lab2/SourceCode/MEMSegReg.v
View file @ d3016199
......@@ -41,7 +41,9 @@ module MEMSegReg(
input wire [11:0] CSRRdE,
output reg [11:0] CSRRdM,
input wire [31:0] CSRWDE,
output reg [31:0] CSRWDM
output reg [31:0] CSRWDM,
input wire MemReadE,
output reg MemReadM
);
initial begin
AluOutM = 0;
......@@ -55,6 +57,7 @@ module MEMSegReg(
CSRWriteM = 1'b0;
CSRRdM = 12'b0;
CSRWDM = 32'b0;
MemReadM = 1'b0;
end
always@(posedge clk)
......@@ -70,6 +73,7 @@ module MEMSegReg(
CSRWriteM <= clear ? 1'b0 : CSRWriteE;
CSRRdM <= clear ? 12'b0 : CSRRdE;