Commit c9e0428e authored by jinbao chen's avatar jinbao chen
Browse files

fix bugs

parent 6ada93d7
......@@ -162,60 +162,72 @@ module RV32Core(
.PCF(PCF)
);
//NO PREDICTION:
/* assign PCF_PRE = 0;
assign PCF_SEL = 0;
assign BTB_FLUSH = BranchE;
assign BTB_PREFAIL = 0;
assign BTB_FILL = 1;
assign BHT_PCE = PCE; */
/* BTB BTB1(
.clk(CPU_CLK),
.rst(CPU_RST),
.PCF(PCF),
// .PCE(PCE),
.BranchTypeE(BranchTypeE),
.BranchE(BranchE),
.BranchTarget(BrNPC),
.Stall(StallF|StallD|StallE),
.Flush(FlushD|FlushE),
.StallD(StallD),
.StallE(StallE),
.FlushD(FlushD),
.FlushE(FlushE),
.PC_PRE(PCF_PRE),
.PC_SEL(PCF_SEL),
.btb_flush(BTB_FLUSH),
.btb_prefail(BTB_PREFAIL),
.btb_fill(BTB_FILL),
.PCE(BHT_PCE)
); */
); */
BHT BHT1(
/* BHT BHT1(
.clk(CPU_CLK),
.rst(CPU_RST),
.PCF(PCF),
//.PCE(PCE),
.BranchTypeE(BranchTypeE),
.BranchE(BranchE),
.BranchTarget(BrNPC),
.Stall(StallF|StallD|StallE),
.Flush(FlushD|FlushE),
.StallD(StallD),
.StallE(StallE),
.FlushD(FlushD),
.FlushE(FlushE),
.PC_PRE(PCF_PRE),
.PC_SEL(PCF_SEL),
.btb_flush(BTB_FLUSH),
.btb_prefail(BTB_PREFAIL),
.btb_fill(BTB_FILL),
.PCE(BHT_PCE)
);
); */
/* PRED PRED1(
PRED PRED1(
.clk(CPU_CLK),
.rst(CPU_RST),
.PCF(PCF),
//.PCE(PCE),
.BranchTypeE(BranchTypeE),
.BranchE(BranchE),
.BranchTarget(BrNPC),
.Stall(StallF|StallD|StallE),
.Flush(FlushD|FlushE),
.StallD(StallD),
.StallE(StallE),
.FlushD(FlushD),
.FlushE(FlushE),
.PC_PRE(PCF_PRE),
.PC_SEL(PCF_SEL),
.flush(BTB_FLUSH),
.prefail(BTB_PREFAIL),
.fill(BTB_FILL),
.PCE(BHT_PCE)
); */
);
// ---------------------------------------------
// ID stage
// ---------------------------------------------
......
......@@ -9,8 +9,10 @@ input wire [31:0] PCF,
input wire [2:0]BranchTypeE,
input wire BranchE,
input wire [31:0] BranchTarget,
input wire Stall,
input wire Flush,
input wire StallD,
input wire StallE,
input wire FlushD,
input wire FlushE,
output wire [31:0] PC_PRE,
output wire PC_SEL,
output wire btb_flush,
......@@ -57,13 +59,17 @@ always@(posedge clk or posedge rst)begin
EXhit <= 0;
PCD <= 0;
PCE <= 0;
end else if(!Stall)begin
IDstat <= Flush?0:IFstat;
IDhit <= Flush?0:btb_hit;
EXstat <= Flush?0:IDstat;
EXhit <= Flush?0:IDhit;
PCD <= PCF;
PCE <= PCD;
end else begin
if(!StallD)begin
IDstat <= FlushD?0:IFstat;
IDhit <= FlushD?0:btb_hit;
PCD <= FlushD?0:PCF;
end
if(!StallE)begin
EXstat <= FlushE?0:IDstat;
EXhit <= FlushE?0:IDhit;
PCE <= FlushE?0:PCD;
end
end
end
......@@ -107,7 +113,7 @@ always @(negedge clk or posedge rst)begin
btb_stat[i] <= 0;
end
end
else if(!Stall)begin
else if(!StallE&&!FlushE)begin
if(EXhit)begin
btb_stat[pce_set] <= next_stat;
end else begin
......
......@@ -9,8 +9,10 @@ input wire [31:0] PCF,
input wire [2:0] BranchTypeE,
input wire BranchE,//FIXME:BRANCH TYPE
input wire [31:0] BranchTarget,
input wire Stall,
input wire Flush,
input wire StallD,
input wire StallE,
input wire FlushD,
input wire FlushE,
output wire [31:0] PC_PRE,
output wire PC_SEL,
output wire btb_flush,
......@@ -59,13 +61,17 @@ always@(posedge clk or posedge rst)begin
EXhit <= 0;
PCD <= 0;
PCE <= 0;
end else if(!Stall)begin
IDstat <= Flush?0:IFstat;
IDhit <= Flush?0:btb_hit;
EXstat <= Flush?0:IDstat;
EXhit <= Flush?0:IDhit;
PCD <= PCF;
PCE <= PCD;
end else begin
if(!StallD)begin
IDstat <= FlushD?0:IFstat;
IDhit <= FlushD?0:btb_hit;
PCD <= FlushD?0:PCF;
end
if(!StallE)begin
EXstat <= FlushE?0:IDstat;
EXhit <= FlushE?0:IDhit;
PCE <= FlushE?0:PCD;
end
end
end
......@@ -88,7 +94,7 @@ always @(negedge clk or posedge rst)begin
btb_stat[i] <= 0;
end
end
else if(!Stall)begin
else if(!StallE&&!FlushE)begin
if(EXhit)begin//TODO:finish this
btb_stat[pce_set] <= next_stat;
end else begin
......
......@@ -9,8 +9,10 @@ input wire [31:0] PCF,
input wire [2:0] BranchTypeE,
input wire BranchE,
input wire [31:0] BranchTarget,
input wire Stall,
input wire Flush,
input wire StallD,
input wire StallE,
input wire FlushD,
input wire FlushE,
output wire [31:0] PC_PRE,
output wire PC_SEL,
output wire flush,
......@@ -32,8 +34,10 @@ BTB #(SET_ADDR_LEN)BTB1(
.BranchE(BranchE),
.BranchTypeE(BranchTypeE),
.BranchTarget(BranchTarget),
.Stall(Stall),//TODO:UPDATE
.Flush(Flush),
.StallD(StallD),//TODO:UPDATE
.StallE(StallE),
.FlushD(FlushD),
.FlushE(FlushE),
.PC_PRE(b_pcpre),
.PC_SEL(b_pcsel),
.btb_flush(b_flush),
......@@ -82,13 +86,17 @@ always @(posedge clk or posedge rst)begin//FIXME:signal passing?
EXhit <= 0;
IDPretaken <= 0;
EXPretaken <= 0;
end else if(!Stall)begin
IDstat <= Flush?0:IFstat;
IDhit <= Flush?0:bht_hit;
EXstat <= Flush?0:IDstat;
EXhit <= Flush?0:IDhit;
IDPretaken <= Flush?0:pre_taken;
EXPretaken <= Flush?0:IDPretaken;
end else begin
if(!StallD)begin
IDstat <= FlushD?0:IFstat;
IDhit <= FlushD?0:bht_hit;
IDPretaken <= FlushD?0:pre_taken;
end
if(!StallE)begin
EXstat <= FlushE?0:IDstat;
EXhit <= FlushE?0:IDhit;
EXPretaken <= FlushE?0:IDPretaken;
end
end
end
......@@ -131,7 +139,7 @@ always @(negedge clk or posedge rst)begin
bht_stat[i] <= 0;
end
end
else if(!Stall)begin
else if(!StallE&&!FlushE)begin
if(EXhit/* &&(|BranchTypeE) */)begin
bht_stat[pce_set] <= next_stat;
end else begin
......
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