Commit 53912a06 authored by jinbao chen's avatar jinbao chen
Browse files

fix bugs

parent c9e0428e
......@@ -10,18 +10,18 @@
// Description: IF-ID Segment Register
//////////////////////////////////////////////////////////////////////////////////
//功能说明
//IDSegReg是IF-ID段寄存器,同时包含了??个同步读写的Bram(此处你可以调用我们提供的InstructionRam??
//它将会自动综合为block memory,你也可以替代�?�的调用xilinx的bram ip核)??
//同步读memory 相当?? 异步读memory 的输出外接D触发器,??要时钟上升沿才能读取数据??
//此时如果再�?�过段寄存器缓存,那么需要两个时钟上升沿才能将数据传递到Ex??
//IDSegReg是IF-ID段寄存器,同时包含了�???个同步读写的Bram(此处你可以调用我们提供的InstructionRam�???
//它将会自动综合为block memory,你也可以替代�?�的调用xilinx的bram ip核)�???
//同步读memory 相当�??? 异步读memory 的输出外接D触发器,�???要时钟上升沿才能读取数据�???
//此时如果再�?�过段寄存器缓存,那么需要两个时钟上升沿才能将数据传递到Ex�???
//因此在段寄存器模块中调用该同步memory,直接将输出传�?�到ID段组合�?�辑
//调用mem模块后输出为RD_raw,�?�过assign RD = stall_ff ? RD_old : (clear_ff ? 32'b0 : RD_raw );
//从�?�实现RD段寄存器stall和clear功能
//实验要求
//补全IDSegReg模块,需补全的片段截取如??
//补全IDSegReg模块,需补全的片段截取如�???
//InstructionRam InstructionRamInst (
// .clk (), //请完善代??
// .addra (), //请完善代??
// .clk (), //请完善代�???
// .addra (), //请完善代�???
// .douta ( RD_raw ),
// .web ( |WE2 ),
// .addrb ( A2[31:2] ),
......@@ -55,8 +55,8 @@ module IDSegReg(
wire [31:0] RD_raw;
/* InstructionRam InstructionRamInst (
.clk (clk), //请完善代??
.addra (A[31:2]), //请完善代??
.clk (clk), //请完善代�???
.addra (A[31:2]), //请完善代�???
.douta ( RD_raw ),
.web ( |WE2 ),
.addrb ( A2[31:2] ),
......@@ -64,7 +64,7 @@ module IDSegReg(
.doutb ( RD2 )
); */
InstructionCacheMM InstCacheInst (
InstructionCacheBTB InstCacheInst (
.clk(clk),
.write_en(|WE2),
.addr(A[31:2]),
......
......@@ -503,6 +503,28 @@ module RV32Core(
.CSRReadE(CSRReadE),
.BTB_FLUSH(BTB_FLUSH)
);
reg [31:0] total_br_cnt;
reg [31:0] err_br_cnt;
always @(negedge CPU_CLK or posedge CPU_RST) begin
if(CPU_RST)begin
total_br_cnt <= 0;
end else /* if(!StallE&&!FlushE) */begin
if(|BranchTypeE)begin
total_br_cnt <= total_br_cnt + 1;
end
end
end
always @(negedge CPU_CLK or posedge CPU_RST) begin
if(CPU_RST)begin
err_br_cnt <= 0;
end else /* if(!StallE) */begin
if(BTB_FLUSH)begin
err_br_cnt <= err_br_cnt + 1;
end
end
end
endmodule
......@@ -98,7 +98,7 @@ module WBSegReg(
end
wire [31:0] RD_raw;
/* DataRam DataCacheInst (
DataRam DataCacheInst (
.clk (clk), //请完善代�?
.wea (WE << A[1:0]), //请完善代�?
.addra (A[31:2]), //请完善代�?
......@@ -109,7 +109,7 @@ module WBSegReg(
.dinb ( WD2 ),
.doutb ( RD2 )
);
assign DCacheMiss = 1'b0; */
assign DCacheMiss = 1'b0;
wire we;
assign we = |WE;
reg [31:0] miss_cnt;
......@@ -148,7 +148,7 @@ always@(posedge clk or posedge rst) begin
end
end
cache_fifo DataCacheInst (
/* cache_fifo DataCacheInst (
.clk (clk),
.rst (rst),
.miss (DCacheMiss),
......@@ -157,7 +157,7 @@ end
.rd_data (RD_raw),
.wr_req (|WE),
.wr_data (WD)
);
); */
// Add clear and stall support
// if chip not enabled, output output last read result
......
......@@ -4,7 +4,7 @@ module cache_fifo #(
parameter LINE_ADDR_LEN = 3, // line内地??????长度,决定了每个line具有2^3个word
parameter SET_ADDR_LEN = 3, // 组地??????长度,决定了??????共有2^3=8??????
parameter TAG_ADDR_LEN = 6, // tag长度
parameter WAY_CNT = 1 // 组相连度,决定了每组中有多少路line,这里是直接映射型cache,因此该参数没用??????
parameter WAY_CNT = 4 // 组相连度,决定了每组中有多少路line,这里是直接映射型cache,因此该参数没用??????
)(
input clk, rst,
output miss, // 对CPU发出的miss信号
......
......@@ -63,7 +63,7 @@ always@(posedge clk or posedge rst)begin
PCE <= 0;
end else begin
if(!StallD)begin
IDstat <= FlushD?0:IFstat;
IDstat <= FlushD?0:PC_SEL;
IDhit <= FlushD?0:btb_hit;
PCD <= FlushD?0:PCF;
end
......@@ -76,8 +76,8 @@ always@(posedge clk or posedge rst)begin
end
assign btb_prefail = EXstat && (!BranchE) &&EXhit;
assign btb_fill = ((!EXstat) && BranchE && EXhit) || (!EXhit && BranchE);
assign btb_prefail = EXstat && (!BranchE);
assign btb_fill = (!EXstat) && BranchE;
assign btb_flush = btb_prefail | btb_fill;
wire next_stat;
......@@ -94,14 +94,14 @@ always @(negedge clk or posedge rst)begin
btb_stat[i] <= 0;
end
end
else if(!StallE&&!FlushE)begin
if(EXhit)begin//TODO:finish this
btb_stat[pce_set] <= next_stat;
else if(!StallE/* &&!(FlushE&&!btb_flush) */)begin
if(btb_prefail)begin//TODO:finish this
btb_stat[pce_set] <= 0;
end else begin
if(|BranchTypeE)begin
if(btb_fill)begin
btb_tags[pce_set] <= pce_tag;
btb_pred[pce_set] <= BranchTarget;
btb_stat[pce_set] <= init_stat;
btb_stat[pce_set] <= 1;
end
end
end
......
......@@ -139,7 +139,7 @@ always @(negedge clk or posedge rst)begin
bht_stat[i] <= 0;
end
end
else if(!StallE&&!FlushE)begin
else if(!StallE/* &&!FlushE */)begin
if(EXhit/* &&(|BranchTypeE) */)begin
bht_stat[pce_set] <= next_stat;
end else begin
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment