Commit 4830cec5 authored by jinbao chen's avatar jinbao chen
Browse files

finish BTB

parent 077dcdfd
......@@ -44,7 +44,262 @@ wire [11:0] addrbl = addrb[13:2];
reg [31:0] ram_cell [0:4095];
initial begin // 可以把测试数据手动输入此处
ram_cell[0] = 32'h00000000;
ram_cell[ 0] = 32'h0000001c;
ram_cell[ 1] = 32'h00000007;
ram_cell[ 2] = 32'h00000053;
ram_cell[ 3] = 32'h00000029;
ram_cell[ 4] = 32'h00000000;
ram_cell[ 5] = 32'h00000050;
ram_cell[ 6] = 32'h00000079;
ram_cell[ 7] = 32'h00000087;
ram_cell[ 8] = 32'h000000cd;
ram_cell[ 9] = 32'h00000058;
ram_cell[ 10] = 32'h000000c5;
ram_cell[ 11] = 32'h0000008b;
ram_cell[ 12] = 32'h0000009f;
ram_cell[ 13] = 32'h0000003a;
ram_cell[ 14] = 32'h0000003b;
ram_cell[ 15] = 32'h00000035;
ram_cell[ 16] = 32'h00000041;
ram_cell[ 17] = 32'h0000009a;
ram_cell[ 18] = 32'h0000009d;
ram_cell[ 19] = 32'h00000001;
ram_cell[ 20] = 32'h0000001a;
ram_cell[ 21] = 32'h0000006f;
ram_cell[ 22] = 32'h000000d2;
ram_cell[ 23] = 32'h0000008f;
ram_cell[ 24] = 32'h00000099;
ram_cell[ 25] = 32'h000000dc;
ram_cell[ 26] = 32'h0000007f;
ram_cell[ 27] = 32'h0000006b;
ram_cell[ 28] = 32'h000000ce;
ram_cell[ 29] = 32'h0000005e;
ram_cell[ 30] = 32'h0000004d;
ram_cell[ 31] = 32'h00000032;
ram_cell[ 32] = 32'h0000002e;
ram_cell[ 33] = 32'h00000013;
ram_cell[ 34] = 32'h0000004f;
ram_cell[ 35] = 32'h000000c6;
ram_cell[ 36] = 32'h00000019;
ram_cell[ 37] = 32'h000000ed;
ram_cell[ 38] = 32'h00000089;
ram_cell[ 39] = 32'h000000f8;
ram_cell[ 40] = 32'h000000be;
ram_cell[ 41] = 32'h000000da;
ram_cell[ 42] = 32'h00000080;
ram_cell[ 43] = 32'h0000002f;
ram_cell[ 44] = 32'h00000097;
ram_cell[ 45] = 32'h00000061;
ram_cell[ 46] = 32'h00000026;
ram_cell[ 47] = 32'h00000017;
ram_cell[ 48] = 32'h00000055;
ram_cell[ 49] = 32'h000000c4;
ram_cell[ 50] = 32'h000000aa;
ram_cell[ 51] = 32'h00000008;
ram_cell[ 52] = 32'h000000d9;
ram_cell[ 53] = 32'h00000018;
ram_cell[ 54] = 32'h00000095;
ram_cell[ 55] = 32'h00000085;
ram_cell[ 56] = 32'h000000a0;
ram_cell[ 57] = 32'h0000004c;
ram_cell[ 58] = 32'h00000076;
ram_cell[ 59] = 32'h0000004e;
ram_cell[ 60] = 32'h000000fd;
ram_cell[ 61] = 32'h00000083;
ram_cell[ 62] = 32'h0000008a;
ram_cell[ 63] = 32'h000000a2;
ram_cell[ 64] = 32'h0000005d;
ram_cell[ 65] = 32'h00000009;
ram_cell[ 66] = 32'h00000062;
ram_cell[ 67] = 32'h00000006;
ram_cell[ 68] = 32'h000000af;
ram_cell[ 69] = 32'h000000a6;
ram_cell[ 70] = 32'h000000f1;
ram_cell[ 71] = 32'h000000d7;
ram_cell[ 72] = 32'h00000072;
ram_cell[ 73] = 32'h000000c1;
ram_cell[ 74] = 32'h000000e1;
ram_cell[ 75] = 32'h000000cc;
ram_cell[ 76] = 32'h0000007e;
ram_cell[ 77] = 32'h00000039;
ram_cell[ 78] = 32'h00000048;
ram_cell[ 79] = 32'h0000002d;
ram_cell[ 80] = 32'h000000bb;
ram_cell[ 81] = 32'h0000007c;
ram_cell[ 82] = 32'h00000004;
ram_cell[ 83] = 32'h000000bf;
ram_cell[ 84] = 32'h00000059;
ram_cell[ 85] = 32'h000000bd;
ram_cell[ 86] = 32'h000000df;
ram_cell[ 87] = 32'h0000007b;
ram_cell[ 88] = 32'h00000049;
ram_cell[ 89] = 32'h0000000c;
ram_cell[ 90] = 32'h0000008c;
ram_cell[ 91] = 32'h000000f3;
ram_cell[ 92] = 32'h000000e7;
ram_cell[ 93] = 32'h00000073;
ram_cell[ 94] = 32'h00000057;
ram_cell[ 95] = 32'h0000001b;
ram_cell[ 96] = 32'h00000052;
ram_cell[ 97] = 32'h00000086;
ram_cell[ 98] = 32'h00000077;
ram_cell[ 99] = 32'h000000e4;
ram_cell[ 100] = 32'h000000a7;
ram_cell[ 101] = 32'h0000005f;
ram_cell[ 102] = 32'h000000f4;
ram_cell[ 103] = 32'h00000024;
ram_cell[ 104] = 32'h00000042;
ram_cell[ 105] = 32'h00000071;
ram_cell[ 106] = 32'h000000eb;
ram_cell[ 107] = 32'h000000f9;
ram_cell[ 108] = 32'h000000b5;
ram_cell[ 109] = 32'h000000c7;
ram_cell[ 110] = 32'h00000065;
ram_cell[ 111] = 32'h00000005;
ram_cell[ 112] = 32'h00000067;
ram_cell[ 113] = 32'h00000063;
ram_cell[ 114] = 32'h00000069;
ram_cell[ 115] = 32'h00000075;
ram_cell[ 116] = 32'h00000064;
ram_cell[ 117] = 32'h000000ab;
ram_cell[ 118] = 32'h000000f2;
ram_cell[ 119] = 32'h000000ef;
ram_cell[ 120] = 32'h00000011;
ram_cell[ 121] = 32'h00000010;
ram_cell[ 122] = 32'h00000098;
ram_cell[ 123] = 32'h00000020;
ram_cell[ 124] = 32'h00000088;
ram_cell[ 125] = 32'h00000033;
ram_cell[ 126] = 32'h0000002c;
ram_cell[ 127] = 32'h000000d6;
ram_cell[ 128] = 32'h000000d5;
ram_cell[ 129] = 32'h0000002b;
ram_cell[ 130] = 32'h000000fe;
ram_cell[ 131] = 32'h000000cb;
ram_cell[ 132] = 32'h0000001e;
ram_cell[ 133] = 32'h00000066;
ram_cell[ 134] = 32'h00000021;
ram_cell[ 135] = 32'h00000027;
ram_cell[ 136] = 32'h00000025;
ram_cell[ 137] = 32'h0000001f;
ram_cell[ 138] = 32'h000000ad;
ram_cell[ 139] = 32'h00000093;
ram_cell[ 140] = 32'h000000fa;
ram_cell[ 141] = 32'h0000004b;
ram_cell[ 142] = 32'h00000046;
ram_cell[ 143] = 32'h00000028;
ram_cell[ 144] = 32'h000000a3;
ram_cell[ 145] = 32'h00000002;
ram_cell[ 146] = 32'h00000051;
ram_cell[ 147] = 32'h00000078;
ram_cell[ 148] = 32'h0000007d;
ram_cell[ 149] = 32'h00000082;
ram_cell[ 150] = 32'h000000ea;
ram_cell[ 151] = 32'h000000e8;
ram_cell[ 152] = 32'h0000003c;
ram_cell[ 153] = 32'h000000e0;
ram_cell[ 154] = 32'h0000006e;
ram_cell[ 155] = 32'h00000030;
ram_cell[ 156] = 32'h0000006d;
ram_cell[ 157] = 32'h000000fb;
ram_cell[ 158] = 32'h000000ec;
ram_cell[ 159] = 32'h000000bc;
ram_cell[ 160] = 32'h00000014;
ram_cell[ 161] = 32'h0000003d;
ram_cell[ 162] = 32'h0000000f;
ram_cell[ 163] = 32'h0000009e;
ram_cell[ 164] = 32'h000000d4;
ram_cell[ 165] = 32'h00000091;
ram_cell[ 166] = 32'h000000b7;
ram_cell[ 167] = 32'h000000c3;
ram_cell[ 168] = 32'h00000043;
ram_cell[ 169] = 32'h0000002a;
ram_cell[ 170] = 32'h0000005b;
ram_cell[ 171] = 32'h000000e9;
ram_cell[ 172] = 32'h00000074;
ram_cell[ 173] = 32'h0000007a;
ram_cell[ 174] = 32'h00000036;
ram_cell[ 175] = 32'h000000f0;
ram_cell[ 176] = 32'h000000b0;
ram_cell[ 177] = 32'h000000ff;
ram_cell[ 178] = 32'h000000b6;
ram_cell[ 179] = 32'h00000015;
ram_cell[ 180] = 32'h00000038;
ram_cell[ 181] = 32'h0000008e;
ram_cell[ 182] = 32'h000000c9;
ram_cell[ 183] = 32'h000000f7;
ram_cell[ 184] = 32'h000000d0;
ram_cell[ 185] = 32'h0000009c;
ram_cell[ 186] = 32'h000000b8;
ram_cell[ 187] = 32'h00000034;
ram_cell[ 188] = 32'h0000006c;
ram_cell[ 189] = 32'h000000d3;
ram_cell[ 190] = 32'h00000045;
ram_cell[ 191] = 32'h00000047;
ram_cell[ 192] = 32'h000000b3;
ram_cell[ 193] = 32'h000000d1;
ram_cell[ 194] = 32'h000000b4;
ram_cell[ 195] = 32'h00000040;
ram_cell[ 196] = 32'h000000dd;
ram_cell[ 197] = 32'h0000005a;
ram_cell[ 198] = 32'h000000a8;
ram_cell[ 199] = 32'h000000e6;
ram_cell[ 200] = 32'h0000005c;
ram_cell[ 201] = 32'h00000068;
ram_cell[ 202] = 32'h00000054;
ram_cell[ 203] = 32'h0000004a;
ram_cell[ 204] = 32'h0000009b;
ram_cell[ 205] = 32'h00000003;
ram_cell[ 206] = 32'h000000d8;
ram_cell[ 207] = 32'h000000a9;
ram_cell[ 208] = 32'h0000003f;
ram_cell[ 209] = 32'h00000056;
ram_cell[ 210] = 32'h0000001d;
ram_cell[ 211] = 32'h00000022;
ram_cell[ 212] = 32'h000000cf;
ram_cell[ 213] = 32'h00000031;
ram_cell[ 214] = 32'h0000000b;
ram_cell[ 215] = 32'h000000db;
ram_cell[ 216] = 32'h000000a5;
ram_cell[ 217] = 32'h00000094;
ram_cell[ 218] = 32'h000000f6;
ram_cell[ 219] = 32'h000000c0;
ram_cell[ 220] = 32'h00000084;
ram_cell[ 221] = 32'h00000012;
ram_cell[ 222] = 32'h000000e2;
ram_cell[ 223] = 32'h0000006a;
ram_cell[ 224] = 32'h000000ac;
ram_cell[ 225] = 32'h0000000e;
ram_cell[ 226] = 32'h000000f5;
ram_cell[ 227] = 32'h0000000a;
ram_cell[ 228] = 32'h000000a1;
ram_cell[ 229] = 32'h00000081;
ram_cell[ 230] = 32'h000000a4;
ram_cell[ 231] = 32'h000000c8;
ram_cell[ 232] = 32'h000000de;
ram_cell[ 233] = 32'h0000000d;
ram_cell[ 234] = 32'h000000ca;
ram_cell[ 235] = 32'h00000096;
ram_cell[ 236] = 32'h000000b2;
ram_cell[ 237] = 32'h00000044;
ram_cell[ 238] = 32'h000000e5;
ram_cell[ 239] = 32'h00000092;
ram_cell[ 240] = 32'h000000ee;
ram_cell[ 241] = 32'h000000ba;
ram_cell[ 242] = 32'h00000023;
ram_cell[ 243] = 32'h00000037;
ram_cell[ 244] = 32'h00000090;
ram_cell[ 245] = 32'h000000b9;
ram_cell[ 246] = 32'h0000008d;
ram_cell[ 247] = 32'h000000c2;
ram_cell[ 248] = 32'h00000016;
ram_cell[ 249] = 32'h000000ae;
ram_cell[ 250] = 32'h000000b1;
ram_cell[ 251] = 32'h000000e3;
ram_cell[ 252] = 32'h000000fc;
ram_cell[ 253] = 32'h00000070;
ram_cell[ 254] = 32'h0000003e;
ram_cell[ 255] = 32'h00000060;
// ......
end
......
......@@ -50,8 +50,8 @@ module EXSegReg(
output reg [1:0] RegReadE,
input wire [2:0] BranchTypeD,
output reg [2:0] BranchTypeE,
input wire [4:0] AluContrlD,
output reg [4:0] AluContrlE,
input wire [3:0] AluContrlD,
output reg [3:0] AluContrlE,
input wire AluSrc1D,
output reg AluSrc1E,
input wire [1:0] AluSrc2D,
......@@ -89,7 +89,7 @@ module EXSegReg(
LoadNpcE = 1'b0;
RegReadE = 2'b00;
BranchTypeE = 3'b0;
AluContrlE = 5'b0;
AluContrlE = 4'b0;
AluSrc1E = 1'b0;
AluSrc2E = 2'b0;
CSRAlusrc1E = 1'b0;
......
......@@ -40,6 +40,7 @@ module HarzardUnit(
input wire [11:0] CSRRdM,
input wire [11:0] CSRRdW,
input wire CSRReadE,CSRWriteE,CSRWriteM,CSRWriteW,
input wire BTB_FLUSH,
output reg [1:0] CSRForwardE
);
wire rs1hitm ;
......@@ -65,7 +66,7 @@ always@(*) begin //checking jump and hazard
{StallF, StallD, StallE, StallM, StallW} <= 5'b11111;
end
else begin
if(BranchE)begin
if(BTB_FLUSH)begin
{FlushF, FlushD, FlushE, FlushM, FlushW} <= 5'b01100;
{StallF, StallD, StallE, StallM, StallW} <= 5'b00000;
end
......
......@@ -10,18 +10,18 @@
// Description: IF-ID Segment Register
//////////////////////////////////////////////////////////////////////////////////
//功能说明
//IDSegReg是IF-ID段寄存器,同时包含了?个同步读写的Bram(此处你可以调用我们提供的InstructionRam?
//它将会自动综合为block memory,你也可以替代?的调用xilinx的bram ip核)?
//同步读memory 相当? 异步读memory 的输出外接D触发器,?要时钟上升沿才能读取数据?
//此时如果再?过段寄存器缓存,那么需要两个时钟上升沿才能将数据传递到Ex?
//因此在段寄存器模块中调用该同步memory,直接将输出传?到ID段组合?
//调用mem模块后输出为RD_raw,?过assign RD = stall_ff ? RD_old : (clear_ff ? 32'b0 : RD_raw );
//从?实现RD段寄存器stall和clear功能
//IDSegReg是IF-ID段寄存器,同时包含了?个同步读写的Bram(此处你可以调用我们提供的InstructionRam?
//它将会自动综合为block memory,你也可以替代�?�的调用xilinx的bram ip核)?
//同步读memory 相当? 异步读memory 的输出外接D触发器,?要时钟上升沿才能读取数据?
//此时如果再�?�过段寄存器缓存,那么需要两个时钟上升沿才能将数据传递到Ex?
//因此在段寄存器模块中调用该同步memory,直接将输出传�?�到ID段组合�?�
//调用mem模块后输出为RD_raw,�?�过assign RD = stall_ff ? RD_old : (clear_ff ? 32'b0 : RD_raw );
//从�?�实现RD段寄存器stall和clear功能
//实验要求
//补全IDSegReg模块,需补全的片段截取如?
//补全IDSegReg模块,需补全的片段截取如?
//InstructionRam InstructionRamInst (
// .clk (), //请完善代?
// .addra (), //请完善代?
// .clk (), //请完善代?
// .addra (), //请完善代?
// .douta ( RD_raw ),
// .web ( |WE2 ),
// .addrb ( A2[31:2] ),
......@@ -55,8 +55,8 @@ module IDSegReg(
wire [31:0] RD_raw;
/* InstructionRam InstructionRamInst (
.clk (clk), //请完善代?
.addra (A[31:2]), //请完善代?
.clk (clk), //请完善代?
.addra (A[31:2]), //请完善代?
.douta ( RD_raw ),
.web ( |WE2 ),
.addrb ( A2[31:2] ),
......
......@@ -10,9 +10,9 @@
// Description: Choose Next PC value
//////////////////////////////////////////////////////////////////////////////////
//功能说明
//NPC_Generator是用来生成Next PC值的模块,根据不同的跳转信号选择不同的新PC?
//NPC_Generator是用来生成Next PC值的模块,根据不同的跳转信号选择不同的新PC?
//输入
//PCF 旧的PC?
//PCF 旧的PC?
//JalrTarget jalr指令的对应的跳转目标
//BranchTarget branch指令的对应的跳转目标
//JalTarget jal指令的对应的跳转目标
......@@ -20,23 +20,36 @@
//JalD==1 ID阶段的Jal指令确定跳转
//JalrE==1 Ex阶段的Jalr指令确定跳转
//输出
//PC_In NPC的??
//PC_In NPC的??
//实验要求
//补全模块
module NPC_Generator(
input wire [31:0] PCF,JalrTarget, BranchTarget, JalTarget,
input wire BranchE,JalD,JalrE,
input wire PCF_SEL,
input wire [31:0] PCF_PRE,
input wire [31:0] PCE,
input wire BTB_FILL,
input wire BTB_PREFAIL,
output reg [31:0] PC_In
);
wire [31:0] PC_raw;
assign PC_raw = PCF + 4;
assign PC_raw = PCF_SEL?PCF_PRE:PCF + 4;
always @(*)
begin
if(BranchE)
begin
PC_In <= BranchTarget;
if(BTB_FILL)begin
PC_In <= BranchTarget;
end else begin
PC_In <= PCF + 4;
end
end
else if(BTB_PREFAIL)
begin
PC_In <= PCE + 4;
end
else if(JalrE)
begin
......
......@@ -114,6 +114,9 @@ module RV32Core(
wire [31:0] CSROperand1;
wire [31:0] CSROperand2;
wire DCacheMiss;
wire PCF_SEL;
wire [31:0] PCF_PRE;
wire BTB_FLUSH;
//wire ICacheMiss;
//wire values assignments
assign {Funct7D, Rs2D, Rs1D, Funct3D, RdD, OpCodeD} = Instr;
......@@ -131,6 +134,9 @@ module RV32Core(
// ---------------------------------------------
// PC-IF
// ---------------------------------------------
wire BTB_PREFAIL;
wire BTB_FILL;
NPC_Generator NPC_Generator1(
.PCF(PCF),
.JalrTarget(AluOutE),
......@@ -139,7 +145,12 @@ module RV32Core(
.BranchE(BranchE),
.JalD(JalD),
.JalrE(JalrE),
.PC_In(PC_In)
.PC_In(PC_In),
.PCF_SEL(PCF_SEL),
.PCF_PRE(PCF_PRE),
.PCE(PCE),
.BTB_FILL(BTB_FILL),
.BTB_PREFAIL(BTB_PREFAIL)
);
IFSegReg IFSegReg1(
......@@ -150,6 +161,20 @@ module RV32Core(
.PCF(PCF)
);
BTB BTB1(
.clk(CPU_CLK),
.rst(CPU_RST),
.PCF(PCF),
.PCE(PCE),
.BranchE(BranchE),
.BranchTarget(BrNPC),
.Stall(StallF|StallD|StallE),
.PC_PRE(PCF_PRE),
.PC_SEL(PCF_SEL),
.btb_flush(BTB_FLUSH),
.btb_prefail(BTB_PREFAIL),
.btb_fill(BTB_FILL)
);
// ---------------------------------------------
// ID stage
// ---------------------------------------------
......@@ -422,7 +447,8 @@ module RV32Core(
.CSRWriteM(CSRWriteM),
.CSRWriteW(CSRWriteW),
.CSRForwardE(CSRForwardE),
.CSRReadE(CSRReadE)
.CSRReadE(CSRReadE),
.BTB_FLUSH(BTB_FLUSH)
);
endmodule
......
......@@ -10,21 +10,21 @@
// Description: Write Back Segment Register
//////////////////////////////////////////////////////////////////////////////////
//功能说明
//WBSegReg是Write Back段寄存器?
//WBSegReg是Write Back段寄存器?
//类似于IDSegReg.V中对Bram的调用和拓展,它同时包含了一个同步读写的Bram
//(此处你可以调用我们提供的InstructionRam,它将会自动综合为block memory,你也可以替代?的调用xilinx的bram ip核)?
//同步读memory 相当? 异步读memory 的输出外接D触发器,?要时钟上升沿才能读取数据?
//此时如果再?过段寄存器缓存,那么需要两个时钟上升沿才能将数据传递到Ex?
//因此在段寄存器模块中调用该同步memory,直接将输出传?到WB段组合?
//调用mem模块后输出为RD_raw,?过assign RD = stall_ff ? RD_old : (clear_ff ? 32'b0 : RD_raw );
//从?实现RD段寄存器stall和clear功能
//(此处你可以调用我们提供的InstructionRam,它将会自动综合为block memory,你也可以替代�?�的调用xilinx的bram ip核)?
//同步读memory 相当? 异步读memory 的输出外接D触发器,?要时钟上升沿才能读取数据?
//此时如果再�?�过段寄存器缓存,那么需要两个时钟上升沿才能将数据传递到Ex?
//因此在段寄存器模块中调用该同步memory,直接将输出传�?�到WB段组合�?�
//调用mem模块后输出为RD_raw,�?�过assign RD = stall_ff ? RD_old : (clear_ff ? 32'b0 : RD_raw );
//从�?�实现RD段寄存器stall和clear功能
//实验要求
//你需要补全WBSegReg模块,需补全的片段截取如?
//你需要补全WBSegReg模块,需补全的片段截取如?
//DataRam DataRamInst (
// .clk (???), //请完善代?
// .wea (???), //请完善代?
// .addra (???), //请完善代?
// .dina (???), //请完善代?
// .clk (???), //请完善代?
// .wea (???), //请完善代?
// .addra (???), //请完善代?
// .dina (???), //请完善代?
// .douta ( RD_raw ),
// .web ( WE2 ),
// .addrb ( A2[31:2] ),
......@@ -34,7 +34,7 @@
//注意事项
//输入到DataRam的addra是字地址,一个字32bit
//请配合DataExt模块实现非字对齐字节load
//请?过补全代码实现非字对齐store
//请�?�过补全代码实现非字对齐store
module WBSegReg(
......@@ -99,17 +99,17 @@ module WBSegReg(
wire [31:0] RD_raw;
/* DataRam DataRamInst (
.clk (clk), //请完善代?
.wea (WE << A[1:0]), //请完善代?
.addra (A[31:2]), //请完善代?
.dina (WD << {A[1:0],3'b0}), //请完善代?
.clk (clk), //请完善代?
.wea (WE << A[1:0]), //请完善代?
.addra (A[31:2]), //请完善代?
.dina (WD << {A[1:0],3'b0}), //请完善代?
.douta ( RD_raw ),
.web ( WE2 ),
.addrb ( A2[31:2] ),
.dinb ( WD2 ),
.doutb ( RD2 )
); */
);
assign DCacheMiss = 1'b0; */
wire we;
assign we = |WE;
reg [31:0] miss_cnt;
......@@ -148,11 +148,11 @@ always@(posedge clk or posedge rst) begin
end
end
cache_lru DataCacheInst (
cache_fifo DataCacheInst (
.clk (clk),
.rst (rst),
.miss (DCacheMiss),
.addr (A[31:0]),//TODO:ADD MEMREAD
.addr (A[31:0]),
.rd_req (MemReadM),
.rd_data (RD_raw),
.wr_req (|WE),
......
module cache_fifo #(
parameter LINE_ADDR_LEN = 3, // line内地?????长度,决定了每个line具有2^3个word
parameter SET_ADDR_LEN = 4, // 组地?????长度,决定了?????共有2^3=8?????
parameter TAG_ADDR_LEN = 5, // tag长度
parameter WAY_CNT = 12 // 组相连度,决定了每组中有多少路line,这里是直接映射型cache,因此该参数没用?????
parameter LINE_ADDR_LEN = 3, // line内地??????长度,决定了每个line具有2^3个word
parameter SET_ADDR_LEN = 3, // 组地??????长度,决定了??????共有2^3=8??????
parameter TAG_ADDR_LEN = 6, // tag长度
parameter WAY_CNT = 3 // 组相连度,决定了每组中有多少路line,这里是直接映射型cache,因此该参数没用??????
)(
input clk, rst,
output miss, // 对CPU发出的miss信号
input [31:0] addr, // 读写请求地址
input rd_req, // 读请求信?????
output reg [31:0] rd_data, // 读出的数据,?????次读?????个word
input wr_req, // 写请求信?????
input [31:0] wr_data // 要写入的数据,一次写?????个word
input rd_req, // 读请求信??????
output reg [31:0] rd_data, // 读出的数据,??????次读??????个word
input wr_req, // 写请求信??????
input [31:0] wr_data // 要写入的数据,一次写??????个word
);
localparam MEM_ADDR_LEN = TAG_ADDR_LEN + SET_ADDR_LEN ; // 计算主存地址长度 MEM_ADDR_LEN,主存大?????=2^MEM_ADDR_LEN个line
localparam UNUSED_ADDR_LEN = 32 - TAG_ADDR_LEN - SET_ADDR_LEN - LINE_ADDR_LEN - 2 ; // 计算未使用的地址的长?????
localparam MEM_ADDR_LEN = TAG_ADDR_LEN + SET_ADDR_LEN ; // 计算主存地址长度 MEM_ADDR_LEN,主存大??????=2^MEM_ADDR_LEN个line
localparam UNUSED_ADDR_LEN = 32 - TAG_ADDR_LEN - SET_ADDR_LEN - LINE_ADDR_LEN - 2 ; // 计算未使用的地址的长??????
localparam LINE_SIZE = 1 << LINE_ADDR_LEN ; // 计算 line ????? word 的数量,????? 2^LINE_ADDR_LEN 个word ????? line
localparam SET_SIZE = 1 << SET_ADDR_LEN ; // 计算?????共有多少组,????? 2^SET_ADDR_LEN 个组
localparam LINE_SIZE = 1 << LINE_ADDR_LEN ; // 计算 line ?????? word 的数量,?????? 2^LINE_ADDR_LEN 个word ?????? line
localparam SET_SIZE = 1 << SET_ADDR_LEN ; // 计算??????共有多少组,?????? 2^SET_ADDR_LEN 个组
reg [ 31:0] cache_mem [SET_SIZE][WAY_CNT][LINE_SIZE]; // SET_SIZE个line,每个line有LINE_SIZE个word
reg [TAG_ADDR_LEN-1:0] cache_tags [SET_SIZE][WAY_CNT]; // SET_SIZE个TAG
reg valid [SET_SIZE][WAY_CNT]; // SET_SIZE个valid(有效?????)
reg valid [SET_SIZE][WAY_CNT]; // SET_SIZE个valid(有效??????)
reg dirty [SET_SIZE][WAY_CNT]; // SET_SIZE个dirty(脏位)
reg [ WAY_CNT:0] cache_fifo [SET_SIZE];
reg [ WAY_CNT:0] way_length [SET_SIZE];
reg [ WAY_CNT:0] swap_out;
wire [ 2-1:0] word_addr; // 将输入地?????addr拆分成这5个部?????
wire [ 2-1:0] word_addr; // 将输入地??????addr拆分成这5个部??????
wire [ LINE_ADDR_LEN-1:0] line_addr;
wire [ SET_ADDR_LEN-1:0] set_addr;
wire [ TAG_ADDR_LEN-1:0] tag_addr;
......@@ -37,8 +37,8 @@ wire [UNUSED_ADDR_LEN-1:0] unused_addr;
wire [ WAY_CNT:0] fifo_pos;
wire [ WAY_CNT:0] queue_len;
enum {IDLE, SWAP_OUT, SWAP_IN, SWAP_IN_OK} cache_stat; // cache 状�?�机的状态定?????
// IDLE代表就绪,SWAP_OUT代表正在换出,SWAP_IN代表正在换入,SWAP_IN_OK代表换入后进行一周期的写入cache操作?????
enum {IDLE, SWAP_OUT, SWAP_IN, SWAP_IN_OK} cache_stat; // cache 状�?�机的状态定??????
// IDLE代表就绪,SWAP_OUT代表正在换出,SWAP_IN代表正在换入,SWAP_IN_OK代表换入后进行一周期的写入cache操作??????
reg [ SET_ADDR_LEN-1:0] mem_rd_set_addr = 0;
reg [ TAG_ADDR_LEN-1:0] mem_rd_tag_addr = 0;
......@@ -95,11 +95,11 @@ always @ (posedge clk or posedge rst) begin // ?? cache ???
if(rd_req) begin // 如果cache命中,并且是读请求,