Commit 007cb530 authored by YouGuoliang's avatar YouGuoliang
Browse files

Add Lab03

parent 6519d3e6
`timescale 1ns / 1ps
module cpu_tb();
reg clk = 1'b1;
reg rst = 1'b1;
always #2 clk = ~clk;
initial #8 rst = 1'b0;
RV32ICore RV32ICore_tb_inst(
.CPU_CLK ( clk ),
.CPU_RST ( rst )
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment