ControlUnit.v 16.2 KB
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: USTC ESLAB 
// Engineer: Wu Yuzhang
// 
// Design Name: RISCV-Pipline CPU
// Module Name: ControlUnit
// Target Devices: Nexys4
// Tool Versions: Vivado 2017.4.1
// Description: RISC-V Instruction Decoder
//////////////////////////////////////////////////////////////////////////////////
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//���ܺͽӿ�˵??
    //ControlUnit       �DZ�CPU��ָ�������������????����·
//����
    // Op               ��ָ��IJ�����???
    // Fn3              ��ָ���func3����
    // Fn7              ��ָ���func7����
//���?
    // JalD==1          ��ʾJalָ���ID����׶�?
    // JalrD==1         ��ʾJalrָ���ID����׶�?
    // RegWriteD        ��ʾID�׶ε�ָ���Ӧ�ļĴ���д���???
    // MemToRegD==1     ��ʾID�׶ε�ָ����Ҫ��data memory��ȡ��???д��Ĵ���?,
    // MemWriteD        ??4bit��Ϊ1�IJ��ֱ�ʾ��Ч������data memory??32bit�ְ�byte����д��,MemWriteD=0001��ʾֻд����??1��byte����xilinx bram�Ľӿ���??
    // LoadNpcD==1      ��ʾ��NextPC�����ResultM
    // RegReadD         ��ʾA1��A2��Ӧ�ļĴ���ֵ�Ƿ�ʹ�õ��ˣ�����forward�Ĵ�??
    // BranchTypeD      ��ʾ��ͬ�ķ�֧���ͣ�??�����Ͷ�����Parameters.v??
    // AluContrlD       ��ʾ��ͬ��ALU���㹦�ܣ��������Ͷ�����Parameters.v??
    // AluSrc2D         ��ʾAlu����??2��???��
    // AluSrc1D         ��ʾAlu����??1��???��
    // ImmType          ��ʾָ������������?
//ʵ��Ҫ��  
    //��ȫģ��  
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`include "Parameters.v"   
module ControlUnit(
    input wire [6:0] Op,
    input wire [2:0] Fn3,
    input wire [6:0] Fn7,
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    input wire [4:0] Rs1D,
    input wire [4:0] RdD,
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    output wire JalD,
    output wire JalrD,
    output reg [2:0] RegWriteD,
    output wire MemToRegD,
    output reg [3:0] MemWriteD,
    output wire LoadNpcD,
    output reg [1:0] RegReadD,
    output reg [2:0] BranchTypeD,
    output reg [3:0] AluContrlD,
    output wire [1:0] AluSrc2D,
    output wire AluSrc1D,
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    output reg CSRAlusrc1D,
    output reg AluOutSrcD,
    output reg CSRWriteD,
    output reg CSRReadD,
    output reg [1:0] CSRAluCtlD,
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    output reg [2:0] ImmType        
    ); 
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reg JalD_reg,JalrD_reg,MemToRegD_reg,LoadNpcD_reg,AluSrc1D_reg;
reg [1:0] AluSrc2D_reg;
assign {JalD,JalrD,MemToRegD,LoadNpcD,AluSrc1D} = {JalD_reg,JalrD_reg,MemToRegD_reg,LoadNpcD_reg,AluSrc1D_reg};
assign AluSrc2D = AluSrc2D_reg;
always @(*) 
if(Op==7'b1110011)
begin//csr
    {JalD_reg,JalrD_reg,MemToRegD_reg,LoadNpcD_reg,AluSrc1D_reg,AluSrc2D_reg} <= 7'b0000000;
    BranchTypeD <= `NOBRANCH;
    MemWriteD <= 4'b0000;
    ImmType <= `ZTYPE;
    AluContrlD <= 4'd11;
    AluOutSrcD <= 1'b1;
    case(Fn3)
    3'b001:
    begin//csrrw
        RegReadD <= 2'b10;
        CSRAlusrc1D <= 1'b0;
        CSRAluCtlD <= `RW;
        CSRReadD <= (RdD==5'b00000)?1'b0:1'b1;
        RegWriteD <= (RdD==5'b00000)?`NOREGWRITE:`LW;
        CSRWriteD <= 1'b1;
    end
    3'b101:
    begin//csrrwi
        RegReadD <= 2'b00;
        CSRAlusrc1D <= 1'b1;
        CSRAluCtlD <= `RW;
        CSRReadD <= (RdD==5'b00000)?1'b0:1'b1;
        RegWriteD <= (RdD==5'b00000)?`NOREGWRITE:`LW;
        CSRWriteD <= 1'b1;
    end
    3'b010:
    begin//csrrs
        RegReadD <= 2'b10;
        CSRAlusrc1D <= 1'b0;
        CSRAluCtlD <= `RS;
        CSRReadD <= 1'b1;
        RegWriteD <= `LW;
        CSRWriteD <= (Rs1D==5'b00000)?1'b0:1'b1;
    end
    3'b110:
    begin//csrrsi
        RegReadD <= 2'b00;
        CSRAlusrc1D <= 1'b1;
        CSRAluCtlD <= `RS;
        CSRReadD <= 1'b1;
        RegWriteD <= `LW;
        CSRWriteD <= 1'b1;
    end
    3'b011:
    begin//csrrc
        RegReadD <= 2'b10;
        CSRAlusrc1D <= 1'b0;
        CSRAluCtlD <= `RC;
        CSRReadD <= 1'b1;
        RegWriteD <= `LW;
        CSRWriteD <= (Rs1D==5'b00000)?1'b0:1'b1;
    end
    3'b111:
    begin//csrrci
        RegReadD <= 2'b00;
        CSRAlusrc1D <= 1'b1;
        CSRAluCtlD <= `RC;
        CSRReadD <= 1'b1;
        RegWriteD <= `LW;
        CSRWriteD <= 1'b1;
    end
    default:
    begin
        RegReadD <= 2'b00;
        CSRAlusrc1D <= 1'b0;
        CSRAluCtlD <= 2'b00;
        CSRReadD <= 1'b0;
        RegWriteD <= `NOREGWRITE;
        CSRWriteD <= 1'b0;
    end
    endcase
end
else
begin
    CSRAlusrc1D <= 1'b0;
    AluOutSrcD <= 1'b0;
    CSRWriteD <= 1'b0;
    CSRAluCtlD <= 2'b00;
    CSRReadD <= 1'b0;
    case(Op)
    7'b0110011:
    begin//Rtype
        {JalD_reg,JalrD_reg,MemToRegD_reg,LoadNpcD_reg,AluSrc1D_reg} <= 5'b00000;
        AluSrc2D_reg <= 2'b00;
        BranchTypeD <= `NOBRANCH;
        MemWriteD <= 4'b0000;//32bit
        ImmType <= `RTYPE;
        case(Fn3)
        3'b000:
        begin
            case(Fn7)
            7'b0000000:
            begin//ADD
                RegWriteD <= `LW;//32bit
                RegReadD <= 2'b11;//2regs
                AluContrlD <= `ADD;
            end
            7'b0100000:
            begin//SUB
                RegWriteD <= `LW;//32bit
                RegReadD <= 2'b11;//2regs
                AluContrlD <= `SUB;
            end
            default:
            begin
                RegWriteD <= `NOREGWRITE;//32bit
                RegReadD <= 2'b00;//2regs
                AluContrlD <= 4'd11;
            end
            endcase
        end 
        3'b001:
        begin
            case(Fn7)
            7'b0000000:
            begin//SLL
                RegWriteD <= `LW;//32bit
                RegReadD <= 2'b11;//2regs
                AluContrlD <= `SLL;
            end
            default:
            begin
                RegWriteD <= `NOREGWRITE;//32bit
                RegReadD <= 2'b00;//2regs
                AluContrlD <= 4'd11;
            end
            endcase
        end
        3'b010:
        begin
            case(Fn7)
            7'b0000000:
            begin//SLT
                RegWriteD <= `LW;//32bit
                RegReadD <= 2'b11;//2regs
                AluContrlD <= `SLT;
            end
            default:
            begin
                RegWriteD <= `NOREGWRITE;//32bit
                RegReadD <= 2'b00;//2regs
                AluContrlD <= 4'd11;
            end
            endcase
        end
        3'b011:
        begin
            case(Fn7)
            7'b0000000:
            begin//SLTU
                RegWriteD <= `LW;//32bit
                RegReadD <= 2'b11;//2regs
                AluContrlD <= `SLTU;
            end
            default:
            begin
                RegWriteD <= `NOREGWRITE;//32bit
                RegReadD <= 2'b00;//2regs
                AluContrlD <= 4'd11;
            end
            endcase
        end
        3'b100:
        begin
            case(Fn7)
            7'b0000000:
            begin//XOR
                RegWriteD <= `LW;//32bit
                RegReadD <= 2'b11;//2regs
                AluContrlD <= `XOR;
            end
            default:
            begin
                RegWriteD <= `NOREGWRITE;//32bit
                RegReadD <= 2'b00;//2regs
                AluContrlD <= 4'd11;
            end
            endcase
        end
        3'b101:
        begin
            case(Fn7)
            7'b0000000:
            begin//SRL
                RegWriteD <= `LW;//32bit
                RegReadD <= 2'b11;//2regs
                AluContrlD <= `SRL;
            end
            7'b0100000:
            begin//SRA
                RegWriteD <= `LW;//32bit
                RegReadD <= 2'b11;//2regs
                AluContrlD <= `SRA;
            end
            default:
            begin
                RegWriteD <= `NOREGWRITE;//32bit
                RegReadD <= 2'b00;//2regs
                AluContrlD <= 4'd11;
            end
            endcase
        end
        3'b110:
        begin
            case(Fn7)
            7'b0000000:
            begin//OR
                RegWriteD <= `LW;//32bit
                RegReadD <= 2'b11;//2regs
                AluContrlD <= `OR;
            end
            default:
            begin
                RegWriteD <= `NOREGWRITE;//32bit
                RegReadD <= 2'b00;//2regs
                AluContrlD <= 4'd11;
            end
            endcase
        end
        3'b111:
        begin
            case(Fn7)
            7'b0000000:
            begin//AND
                RegWriteD <= `LW;//32bit
                RegReadD <= 2'b11;//2regs
                AluContrlD <= `AND;
            end
            default:
            begin
                RegWriteD <= `NOREGWRITE;//32bit
                RegReadD <= 2'b00;//2regs
                AluContrlD <= 4'd11;
            end
            endcase
        end
        default:
        begin
            RegWriteD <= `NOREGWRITE;//32bit
            RegReadD <= 2'b00;//
            AluContrlD <= 4'd11;
        end
        endcase
    end
    7'b0010011:
    begin//Itype
        if(Fn3==3'b001)
        begin
            {JalD_reg,JalrD_reg,MemToRegD_reg,LoadNpcD_reg,AluSrc1D_reg} <= 5'b00000;
            AluSrc2D_reg <= 2'b01;
            BranchTypeD <= `NOBRANCH;
            MemWriteD <= 4'b0000;//32bit
            ImmType <= `RTYPE;
            case(Fn7)
            7'b0000000:
            begin//SLLI
                RegWriteD <= `LW;//32bit
                RegReadD <= 2'b10;//
                AluContrlD <= `SLL;
            end
            default:
            begin
                RegWriteD <= `NOREGWRITE;//32bit
                RegReadD <= 2'b00;//
                AluContrlD <= 4'd11;
            end
            endcase
        end
        else if(Fn3==3'b101)
        begin
            {JalD_reg,JalrD_reg,MemToRegD_reg,LoadNpcD_reg,AluSrc1D_reg} <= 5'b00000;
            AluSrc2D_reg <= 2'b01;
            BranchTypeD <= `NOBRANCH;
            MemWriteD <= 4'b0000;//32bit
            ImmType <= `RTYPE;
            case(Fn7)
            7'b0000000:
            begin//SRLI
                RegWriteD <= `LW;//32bit
                RegReadD <= 2'b10;//
                AluContrlD <= `SRL;
            end
            7'b0100000:
            begin//SRAI
                RegWriteD <= `LW;//32bit
                RegReadD <= 2'b10;//
                AluContrlD <= `SRA;
            end
            default:
            begin
                RegWriteD <= `NOREGWRITE;//32bit
                RegReadD <= 2'b00;//
                AluContrlD <= 4'd11;
            end
            endcase
        end
        else
        begin
            {JalD_reg,JalrD_reg,MemToRegD_reg,LoadNpcD_reg,AluSrc1D_reg} <= 5'b00000;
            AluSrc2D_reg <= 2'b10;
            BranchTypeD <= `NOBRANCH;
            MemWriteD <= 4'b0000;//32bit
            //RegWriteD <= `LW;//32bit
            //RegReadD <= 2'b10;//rs1
            ImmType <= `ITYPE;
            case(Fn3)
            3'b000:
            begin//ADDI
                AluContrlD <= `ADD;
                RegWriteD <= `LW;
                RegReadD <= 2'b10;
            end
            3'b010:
            begin
                AluContrlD <= `SLT;
                RegWriteD <= `LW;
                RegReadD <= 2'b10;
            end
            3'b011:
            begin
                AluContrlD <= `SLTU;
                RegWriteD <= `LW;
                RegReadD <= 2'b10;
            end
            3'b100:
            begin
                AluContrlD <= `XOR;
                RegWriteD <= `LW;
                RegReadD <= 2'b10;
            end
            3'b110:
            begin
                AluContrlD <= `OR;
                RegWriteD <= `LW;
                RegReadD <= 2'b10;
            end
            3'b111:
            begin
                AluContrlD <= `AND;
                RegWriteD <= `LW;
                RegReadD <= 2'b10;
            end
            default:
            begin
                AluContrlD <= 4'd11;
                RegWriteD <= `NOREGWRITE;
                RegReadD <= 2'b00;
            end
            endcase                
        end
    end
    7'b0100011:
    begin//stype
        {JalD_reg,JalrD_reg,MemToRegD_reg,LoadNpcD_reg,AluSrc1D_reg} <= 5'b00000;
        AluSrc2D_reg <= 2'b10;//imm
        BranchTypeD <= `NOBRANCH;
        //MemWriteD <= 4'b0000;//32bit
        RegWriteD <= `NOREGWRITE;//32bit
        RegReadD <= 2'b11;//rs1 rs2
        ImmType <= `STYPE;
        AluContrlD <= `ADD;
        case(Fn3)
        3'b000:
        begin//store byte
            MemWriteD <= 4'b0001;
        end
        3'b001:
        begin//store half word
            MemWriteD <= 4'b0011;
        end
        3'b010:
        begin//store word
            MemWriteD <= 4'b1111;
        end
        default:
        begin
            MemWriteD <= 4'b0000;
        end
        endcase
    end
    7'b0000011:
    begin//load
        {JalD_reg,JalrD_reg,MemToRegD_reg,LoadNpcD_reg,AluSrc1D_reg} <= 5'b00100;
        AluSrc2D_reg <= 2'b10;//imm
        BranchTypeD <= `NOBRANCH;
        MemWriteD <= 4'b0000;//32bit
        //RegWriteD <= `NOREGWRITE;//32bit
        RegReadD <= 2'b10;//rs1
        ImmType <= `ITYPE;
        AluContrlD <= `ADD;
        case(Fn3)
        3'b000:
        begin//load byte
            RegWriteD <= `LB;
        end
        3'b001:
        begin
            RegWriteD <= `LH;
        end
        3'b010:
        begin
            RegWriteD <= `LW;
        end
        3'b100:
        begin
            RegWriteD <= `LBU;
        end
        3'b101:
        begin
            RegWriteD <= `LHU;
        end
        default:
            RegWriteD <= `NOREGWRITE;
        endcase
    end
    7'b1100011:
    begin//branch
        {JalD_reg,JalrD_reg,MemToRegD_reg,LoadNpcD_reg,AluSrc1D_reg} <= 5'b00000;
        AluSrc2D_reg <= 2'b00;
        //BranchTypeD <= `NOBRANCH;
        MemWriteD <= 4'b0000;//32bit
        RegWriteD <= `NOREGWRITE;//32bit
        RegReadD <= 2'b11;//rs1 rs2
        ImmType <= `BTYPE;
        AluContrlD <= 4'd11;
        case(Fn3)
        3'b000:
        begin
            BranchTypeD <= `BEQ;
        end
        3'b001:
        begin
            BranchTypeD <= `BNE;
        end
        3'b100:
        begin
            BranchTypeD <= `BLT;
        end
        3'b101:
        begin
            BranchTypeD <= `BGE;
        end
        3'b110:
        begin
            BranchTypeD <= `BLTU;
        end
        3'b111:
        begin
            BranchTypeD <= `BGEU;
        end
        default:
        begin
            BranchTypeD <= `NOBRANCH;
        end
        endcase
    end
    7'b1100111:
    begin//jalr
        {JalD_reg,JalrD_reg,MemToRegD_reg,LoadNpcD_reg,AluSrc1D_reg} <= 5'b01010;
        AluSrc2D_reg <= 2'b10;//imm
        BranchTypeD <= `NOBRANCH;
        MemWriteD <= 4'b0000;//32bit
        RegWriteD <= `LW;//32bit
        RegReadD <= 2'b10;//rs1
        ImmType <= `ITYPE;
        AluContrlD <= `ADD;
    end
    7'b1101111:
    begin//jal
        {JalD_reg,JalrD_reg,MemToRegD_reg,LoadNpcD_reg,AluSrc1D_reg} <= 5'b10010;
        AluSrc2D_reg <= 2'b00;//no rs2
        BranchTypeD <= `NOBRANCH;
        MemWriteD <= 4'b0000;//32bit
        RegWriteD <= `LW;//32bit
        RegReadD <= 2'b00;//
        ImmType <= `JTYPE;
        AluContrlD <= 4'd11;
    end
    7'b0010111:
    begin//AUIPC
        {JalD_reg,JalrD_reg,MemToRegD_reg,LoadNpcD_reg,AluSrc1D_reg} <= 5'b00001;
        AluSrc2D_reg <= 2'b10;//imm
        BranchTypeD <= `NOBRANCH;
        MemWriteD <= 4'b0000;//32bit
        RegWriteD <= `LW;//32bit
        RegReadD <= 2'b00;//
        ImmType <= `UTYPE;
        AluContrlD <= `ADD;
    end
    7'b0110111:
    begin
        {JalD_reg,JalrD_reg,MemToRegD_reg,LoadNpcD_reg,AluSrc1D_reg} <= 5'b00000;
        AluSrc2D_reg <= 2'b10;//imm
        BranchTypeD <= `NOBRANCH;
        MemWriteD <= 4'b0000;//32bit
        RegWriteD <= `LW;//32bit
        RegReadD <= 2'b00;//
        ImmType <= `UTYPE;
        AluContrlD <= `LUI;
    end
    default:
    begin
        {JalD_reg,JalrD_reg,MemToRegD_reg,LoadNpcD_reg,AluSrc1D_reg} <= 5'b00000;
        AluSrc2D_reg <= 2'b00;
        BranchTypeD <= `NOBRANCH;
        MemWriteD <= 4'b0000;//32bit
        RegWriteD <= `NOREGWRITE;//32bit
        RegReadD <= 2'b00;//
        ImmType <= `RTYPE;
        AluContrlD <= 4'd11;
    end
    endcase    
end
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endmodule