CSRF.v 469 Bytes
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`timescale 1ns / 1ps

module CSRF (
    input clk,
    input rst,
    input WE,
    input wire [11:0] WA,
    input wire [31:0] WD,
    input wire [11:0] RA,
    output wire[31:0] RD
);

reg [31:0] CSR[4095:0];
integer i;

always@(negedge clk or posedge rst)
begin
    if(rst) begin
        for(i=0;i<4096;i=i+1)
            CSR[i][31:0] <= 32'b0;
    end 
    else if((WA[11:10]!=2'b11)&&WE) begin
        CSR[WA] <=  WD;  
    end 
end
assign RD = CSR[RA];
endmodule