Explore projects
-
-
-
-
-
-
-
-
-
-
-
-
-
This repository belongs to UltraMIPS_NSCSCC, and consists of the development of pipeline Cache(ICache/DCache) and associated components for dual-issue cpu.
Updated -
MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
Updated -
a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
Updated -
he xu / Sirius
GNU General Public License v3.0 or laterAsymmetric dual issue in-order microprocessor.
Updated -
Updated
-
Updated
-
he xu / nontrivial-mips
MIT LicenseNonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
Updated -