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a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
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This repository belongs to UltraMIPS_NSCSCC, and consists of the development of pipeline Cache(ICache/DCache) and associated components for dual-issue cpu.
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he xu / nontrivial-mips
MIT LicenseNonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
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