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  • r9a07g044.dtsi
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  • Biju Das's avatar
    dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitions · c3e67ad6
    Biju Das authored Jun 26, 2021
    
    
    Update clock and reset definitions as per RZ/G2L_clock_list_r02_02.xlsx
    and RZ/G2L HW(Rev.0.50) manual.
    
    Update {GIC,IA55,SCIF} clock and reset entries in the CPG driver, and
    separate reset from module clocks in order to handle them efficiently.
    
    Update the SCIF0 clock and reset index in the SoC DTSI.
    
    Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
    Reviewed-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
    Link: https://lore.kernel.org/r/20210626081344.5783-6-biju.das.jz@bp.renesas.com
    Link: https://lore.kernel.org/r/20210626081344.5783-7-biju.das.jz@bp.renesas.com
    Link: https://lore.kernel.org/r/20210626081344.5783-8-biju.das.jz@bp.renesas.com
    
    
    [geert: Squashed 3 commits]
    Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
    c3e67ad6