Commit a2e0f10b authored by yz w's avatar yz w
Browse files

'add_lab3'

parent 74866097
`timescale 1ns / 1ps
module cpu_tb();
reg clk = 1'b1;
reg rst = 1'b1;
always #2 clk = ~clk;
initial #8 rst = 1'b0;
RV32ICore RV32ICore_tb_inst(
.CPU_CLK ( clk ),
.CPU_RST ( rst )
);
endmodule
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